1. Field of the Invention
The present invention relates to multipliers on programmable chips. In one example, the present invention relates to methods and apparatus for providing a multiplier that can also perform shifting, rotation operations, and other logic operations.
2. Description of Related Art
A variety of hard coded logic blocks are often provided along with configurable logic elements on programmable chips in order to improve programmable chip performance. Processing performed using dedicated hard coded logic is often more efficient than processing performed using soft coded logic. However, provided additional hard coded logic on a programmable chip can lead to added cost, increased waste, and decreased configurability.
For example, a large number of multipliers may be provided in hard coded logic, but a designer may only need a limited number of multipliers. Mechanisms for more efficiently using hard coded logic are limited. Consequently, there are continued efforts to provide devices that overcome at least some of the drawbacks noted above.